1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor package at wafer level, and more particularly to a method for fabricating a micro device package with a cavity.
2. Description of the Related Art
As electronic devices have become smaller and thinner, the speed and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher packaging efficiency. Demand for miniaturization is the primary catalyst driving the usage of advanced packages such as chip scale packages (CSP) and flip chips. Both of them greatly increase the packaging efficiency and reduce the amount of board real estate required when compared with the alternative ball grid array (BGA) and thin small outline package (TSOP). Therefore, recently both of techniques have been applied to the packaging of the micro device.
Referring now to FIG. 1, it depicts a conventional micro device package 5. The package 5 mainly includes a chip 1 and an electric circuit substrate 2. The chip 1 has a micro device 16 electrically connected to bonding pads 12a on the chip 1. The electric circuit substrate 2 has a top and a bottom surfaces, and the top surface of the electric circuit substrate 2 has a plurality of bonding pads 12b corresponding to bonding pads 12a on the chip 1 and conductive bumps 14 for electrically connecting the bonding pads 12b and the bonding pads 12a. A plurality of solder bumps 3 are disposed on the bottom surface of the electric circuit substrate 2 which is constructed to a single layer or multiple layers for rearranging the bonding pads 12b and electrically connected the bonding pads 12b to the solder bumps 3. The rearrangement of the pads is useful for electrically connecting the micro device package 5 to a motherboard (not shown). A flow-type or no-flow-type underfill material 31 is filled outside the conductive bumps 14 between the chip 1 and the substrate 2 to increase the lifetime of the conductive bumps 14.
However, the conventional micro device package has some drawbacks. One of the drawbacks is that in comparison with wafer level packaging process, the throughput of the conventional packaging is low and the surface contamination of the wafers is high, because the package is encapsulated after the dicing of the wafers. Furthermore, the pitch of the rearranged electric pads of the conventional package (the distance between the adjacent solder bumps 3 as shown in FIG. 1) is larger than the pitch of the bonding pads 12a on the chip 1 (the distance between the adjacent bonding pads 12a as shown in FIG. 1) so as to hinder the high density application of element or circuit. In addition, the process of the underfill material 31 by flowing is a low throughput process, so the packaging efficiency is further decreased.
Accordingly, there exists a need for a method for manufacturing a micro device package at the wafer level so as to solve the above mentioned problems and disadvantages.
It is a object of the present invention to provide a micro device package with a cavity, which is fabricated at the wafer level and is small in dimension.
It is another object of the present invention to provide a method for mass-produced a package with a cavity at wafer-level to greatly increase the throughput of the packaging.
To achieve the object mentioned above, the present invention provides a wafer-level package with a cavity including a chip, a substrate, and a seal member. The chip has a micro device and a plurality of bonding pads electrically connected to the micro device. The substrate has a plurality of through conductive vias corresponding and electrically connected to the bonding pads. Each of the bonding pads on the chip is provided with a conductive bump for electrically connecting the bonding pad to the conductive via. The seal member surrounds the package to form a hermetical cavity.
The present invention further provides a method for fabricating a package with a cavity at wafer-level, comprising the steps of: (a) providing a wafer including a plurality of chips being separated from each other by scribe lines and each having a plurality of bonding pads; (b) forming a plurality of conductive bumps on the bonding pads of the chips; (c) forming a seal member surrounding each of the chips on the wafer; (d) providing a substrate having the scribe lines corresponding to the scribe lines of the wafer; (e) forming a plurality of conductive vias on the substrate corresponding to the plurality of bonding pads of the chips on the wafer; (f) aligning and bonding the wafer and the substrate together so that a plurality of the conductive bumps on the wafer are respectively electrically connected to the conductive vias of the substrate, and the seal member is disposed between the wafer and the substrate to form a plurality of hermetical cavities; and (g) dicing the bonded the wafer and the substrate to form the individual package.
A wafer-level package with a cavity according to the present invention is characterized that the through vias directly formed in the cap wafer are a type of an electric feed through interconnection structure and the pitch of the conductive vias in the said structure equals to the pitch of the bonding pads on the base wafer, whereby the density of the element of circuit can be increased. In addition, not only does the wafer-level packaging enhance the packaging efficiency, but also the conventional flowed encapsulated process is replaced with the pre-depositing seal member around the base wafer, and thus the packaging efficiency can be further enhanced.